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Backend Target Dataflow Signals
Backend Target Dataflow Signals
The additional signals in Table 5-4 are used only for Target data transfers between the core and the user’s backend logic.
These signals only function when the TARGET parameter is set. All these inputs and outputs are synchronous to the
PCI clock.
Table 5-4 · Target Mode Control Signals
Name
Type
Width
Description
Active high input indicating that the backend controller cannot complete the current transfer.
BUSY
Input
1
When BUSY is asserted, the core may perform a PCI retry, a disconnect without data, or a
disconnect with data cycle, depending on the state of the internal pipeline and the backend
WR_BE_RDY and RD_STB_IN signals.
ERROR
EXT_INTN
INTAN_OUT
Input
Input
Output
1
1
1
Active high signal that will force the PCI core to terminate the current transfer with a Target abort
cycle. Once asserted, ERROR must be held active until DP_DONE occurs.
Active low interrupt from the backend. When PCI interrupts are enabled, this will cause an
INTAN signal to be asserted.
Active low output indicating the status of the PCI INTAN signal. This allows the backend logic to
respond to an interrupt from another PCI device that has asserted INTAN.
v4.0
47
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